This application claims benefit of priority under 35USC xc2xa7119 to Japanese Patent Application No. Hei 11-350841(1999), filed on Dec. 9, 1999, the entire contents of which are incorporated by reference herein.
This invention relates to a nonvolatile semiconductor memory device and its manufacturing method.
There is known an electrically rewritable, nonvolatile semiconductor memory (EEPROM: electrically erasable and programmable read-only-memory) using memory cells of a stacked-gate structure stacking floating gates and control gates. This kind of EEPROM uses a tunneling insulation film as a first gate insulating film between floating gates and a semiconductor substrate and typically uses, as the second gate insulating film between floating gates and control gates, an ONO film which is a multi-layered film of a silicon oxide film (O) on a silicon nitride film (N) on a silicon oxide film (O).
Each memory cell is formed in an element-forming region partitioned by an element isolation/insulation film. In general, a floating gate electrode film is divided in the direction of control gate line (word line) by making a slit on the element isolation/insulation film. In the step of making the slit, division of floating gates in the bit-line direction is not yet done. Then a control gate electrode film is stacked via an ONO film on all surfaces of the substrate including the top of the slit-processed floating gate electrode film, and by sequentially etching the control gate electrode film, ONO film, and floating gate electrode film, control gates and floating gates are isolated in the bit-line direction. After that, source and drain diffusion layers are formed in self-alignment with the control gates.
In the above-introduced conventional EEPROM structure, floating gates of memory cells adjacent in the word-line direction are isolated on the element isolation/insulation film, but the ONO film formed thereon is continuously made in the word-line direction. It is already known that, if the isolation width (slit width) of floating gates in the word-line direction is narrowed by miniaturization of memory cells, this structure is subject to movements of electric charges through the ONO film when there is a difference in charge storage status between adjacent floating gates. This is because electric charges are readily movable in the lateral direction in the silicon nitride film or along the boundaries between the silicon nitride film and the silicon oxide films of the ONO film. Therefore, in microminiaturized EEPROM, when adjacent memory cells in the word-line direction have different data states, their threshold values vary due to movements of electric charges, and often result in destruction of data.
It is therefore an object of the invention to provide a nonvolatile semiconductor memory device improved in reliability by preventing destruction of data caused by movements of electric charges between floating gates, and also relates to its manufacturing method.
According to the first aspect of the invention, there is provided a nonvolatile semiconductor memory device comprising:
a semiconductor substrate;
a plurality of element-forming regions partitioned by element isolation/insulation films in said semiconductor substrate;
floating gates formed in said element-forming regions via a first gate insulating film and separated for individual said element-forming regions;
second gate insulating films formed on said floating gates, and divided and separated above said element isolation/insulation films;
control gates formed on said floating gates via said second gate insulating films; and
source and drain diffusion layers formed in self-alignment with said control gates.
According to the second aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a semiconductor substrate;
a plurality of element-forming regions partitioned by element isolation/insulation films in said semiconductor substrate;
floating gates formed in said element-forming regions via a first gate insulating film and separated for individual said element-forming regions;
a second gate insulating film formed on said floating gates to continuously extend over a plurality of element-forming regions along recesses made into surfaces of said element isolation/insulation films;
control gates formed on said floating gates via said second gate insulating film; and
source and drain diffusion layers formed in self-alignment with said control gates.
According to the third aspect of the present invention, there is provided a manufacturing method of a nonvolatile semiconductor memory device, comprising the steps of:
making element isolation/insulation films that partition element-forming regions in a semiconductor substrate;
stacking a first gate electrode material film and a second gate insulating film on said semiconductor substrate via a first gate insulating film;
etching said second gate insulating film and the underlying first gate electrode material film to make slits that separate said first gate electrode material film above said element isolation/insulation films;
forming an insulating film on side surfaces of said first gate electrode material film, and thereafter stacking a second gate electrode material film;
sequentially etching said second gate electrode material film, said second gate insulating film and said first gate electrode material film to pattern said first gate electrode film into floating gates and said second gate electrode material film into control gates; and
making source and drain diffusion layers in self alignment with said control gates.
According to the fourth aspect of the present invention, there is provided a manufacturing method of a nonvolatile semiconductor memory device, comprising the steps of:
making element isolation/insulation films that partition element-forming regions in a semiconductor substrate;
stacking a first gate electrode material film and a second gate insulating film on said semiconductor substrate via a first gate insulating film;
etching said second gate insulating film and the underlying first gate electrode material film to make slits that separate said first gate electrode material film above said element isolation/insulation films;
sequentially stacking a third gate insulating film and a second gate electrode material film;
sequentially etching said second gate electrode material film, said third and second gate insulating films, and said first gate electrode material film to pattern said first gate electrode material film into floating gates and said second gate electrode material film into control gates; and
making source and drain diffusion layers in self-alignment with said control gates.
According to the fourth aspect of the present invention, there is provided a manufacturing method of a nonvolatile semiconductor memory device, comprising the steps of:
making element isolation/insulation films that partition element-forming regions in a semiconductor substrate;
stacking a first gate electrode material film on said semiconductor substrate via a first gate insulating film;
etching said first gate electrode material film to make slits that separate said first gate electrode material film on said element isolation/insulation films;
etching surfaces of said element isolation/insulation films exposed to said slits to make recesses;
stacking a second gate electrode material film on said first gate electrode material film and said element isolation/insulation films via said first gate insulating film;
sequentially etching said second gate electrode material film, said gate insulating film and said first gate electrode material film to pattern said first gate electrode material film into floating gates and said second gate electrode material film into control gates; and
making source and drain diffusion layers in self-alignment with said control gates.
According to the invention, by isolating the second gate insulating film between the floating gates and the control gates in a region between adjacent memory cells via an element isolation/insulation film, electric charges are prevented from moving between adjacent floating gates via the second gate insulating film.
Furthermore, even when the second gate insulating film is not completely isolated on the device isolation film, if a recess is made on the surface of the element isolation/insulation film to have the second gate insulting film extend along the recess, it is substantially equivalent to an increase of the distance between adjacent floating gates, and here again results in preventing movements of electric charges between adjacent floating gates.
Therefore, also when memory cells are miniaturized, the invention prevents data destruction due to movements of electric charges and improves the reliability.